In recent years, the storage capacity of a semiconductor device is increasing year by year due to miniaturizations of a memory cell and a peripheral circuit. Along with the increase in the storage capacity, however, the risk of inclusion of a defective memory cell also increases. Then, technologies have been proposed in which, by including a normal memory cell and a redundant memory cell to be used when a defect has been detected in the normal memory cell, the normal memory cell with the defect detected therein (hereinafter referred to as a defective memory cell) is relieved (as in JP2011-233631A (Patent Literature 1), JP2006-147030A (Patent Literature 2). JP2006-179114A (Patent Literature 3) and JP2003-288795A (Patent Literature 4)). Specifically, in the technologies disclosed in Patent Literatures 1 to 4, the defective memory cell is replaced with the redundant memory cell, thereby relieving the defective memory cell.
Each disclosure of the above-listed Patent Literature is incorporated herein by reference in its entirety.